Vivado_HLSのcsimは動作するけどcosimが終了しない場合の原因と対処方法

タイトルの通り、Vivado_HLSでcsimは期待通りに動作するけど、 C/RTL協調シミュレーション(cosim)でいつまで経ってもシミュレーションが終了しない場合の原因と対処方法。高位合成でカウンタ作ったときとか、うっかりやりがちかも。

結論

関数が呼び出された際に、出力ポートで代入処理が行われないパスを通っているので、代入されるようにすれば良い。だめな信号の見つけ方は次回。

再現コード

事象を再現するコードは以下の仕様。 

合成対象：zeppeli
ポート：
in[0:0]: bread_i
out[7:0]: bread_num_o
動作：
bread_num_oに今まで入力されたbread_iの数を出力する。255を超えると0になる。

実装：
zeppeli.h

#ifndef ZEPPELI
#define ZEPPELI

void zeppeli(
    ap_uint<1>  bread_i,
    ap_uint<8>  *bread_num_o
);

#endif

zeppeli.cpp

#include <stdint.h>
#include <ap_int.h>
#include "zeppeli.h"

void zeppeli(
        ap_uint<1>  bread_i,
        ap_uint<8>  *bread_num_o
){
#pragma HLS INTERFACE s_axilite register port=bread_num_o
    static ap_uint<8> bread_num = 0;
    if(bread_i == 1){
        ++bread_num;
        *bread_num_o = bread_num;
    }
}

tb_zeppeli.cpp

#include <stdint.h>
#include <ap_int.h>
#include "zeppeli.h"

int main(int argc, char **argv){
    ap_uint<8> bread_num;
    zeppeli(0,&bread_num);
    return 0;
}

csim実行結果

こちらは正常に完了する。

Starting C simulation ...
/opt/Xilinx/Vivado/2019.2/bin/vivado_hls /home/akira/work/test/zeppeli/zeppeli/solution1/csim.tcl
INFO: [HLS 200-10] Running '/opt/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/vivado_hls'
INFO: [HLS 200-10] For user 'akira' on host 'akira-Surface-Book' (Linux_x86_64 version 5.4.0-48-generic) on Tue Oct 13 00:21:29 JST 2020
INFO: [HLS 200-10] On os Ubuntu 18.04.5 LTS
INFO: [HLS 200-10] In directory '/home/akira/work/test/zeppeli'
Sourcing Tcl script '/home/akira/work/test/zeppeli/zeppeli/solution1/csim.tcl'
INFO: [HLS 200-10] Opening project '/home/akira/work/test/zeppeli/zeppeli'.
INFO: [HLS 200-10] Opening solution '/home/akira/work/test/zeppeli/zeppeli/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-10] Setting target device to 'xczu3eg-sbva484-1-e'
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
   Compiling ../../../../tb_zeppeli.cpp in debug mode
   Compiling ../../../../zeppeli.cpp in debug mode
   Generating csim.exe
INFO: [SIM 211-1] CSim done with 0 errors.
INFO: [SIM 211-3] *************** CSIM finish ***************
Finished C simulation.

cosim実行結果(エラー)

見ての通り終わらない。

Starting C/RTL cosimulation ...
/opt/Xilinx/Vivado/2019.2/bin/vivado_hls /home/akira/work/test/zeppeli/zeppeli/solution1/cosim.tcl
INFO: [HLS 200-10] Running '/opt/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/vivado_hls'
INFO: [HLS 200-10] For user 'akira' on host 'akira-Surface-Book' (Linux_x86_64 version 5.4.0-48-generic) on Tue Oct 13 00:23:41 JST 2020
INFO: [HLS 200-10] On os Ubuntu 18.04.5 LTS
INFO: [HLS 200-10] In directory '/home/akira/work/test/zeppeli'
Sourcing Tcl script '/home/akira/work/test/zeppeli/zeppeli/solution1/cosim.tcl'
INFO: [HLS 200-10] Opening project '/home/akira/work/test/zeppeli/zeppeli'.
INFO: [HLS 200-10] Opening solution '/home/akira/work/test/zeppeli/zeppeli/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-10] Setting target device to 'xczu3eg-sbva484-1-e'
INFO: [COSIM 212-47] Using XSIM for RTL simulation.
INFO: [COSIM 212-14] Instrumenting C test bench ...
   Build using "/opt/Xilinx/Vivado/2019.2/tps/lnx64/gcc-6.2.0/bin/g++"
   Compiling apatb_zeppeli.cpp
   Compiling zeppeli.cpp_pre.cpp.tb.cpp
   Compiling tb_zeppeli.cpp_pre.cpp.tb.cpp
   Generating cosim.tv.exe
INFO: [COSIM 212-302] Starting C TB testing ...
INFO: [COSIM 212-333] Generating C post check test bench ...
INFO: [COSIM 212-12] Generating RTL test bench ...
INFO: [COSIM 212-1] *** C/RTL co-simulation file generation completed. ***
INFO: [COSIM 212-323] Starting verilog simulation.
INFO: [COSIM 212-15] Starting XSIM ...
INFO: [XSIM 43-3496] Using init file passed via -initfile option "/opt/Xilinx/Vivado/2019.2/data/xsim/ip/xsim_ip.ini".
Vivado Simulator 2019.2
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab xil_defaultlib.apatb_zeppeli_top glbl -prj zeppeli.prj -L smartconnect_v1_0 -L axi_protocol_checker_v1_1_12 -L axi_protocol_checker_v1_1_13 -L axis_protocol_checker_v1_1_11 -L axis_protocol_checker_v1_1_12 -L xil_defaultlib -L unisims_ver -L xpm --initfile /opt/Xilinx/Vivado/2019.2/data/xsim/ip/xsim_ip.ini --lib ieee_proposed=./ieee_proposed -s zeppeli
Multi-threading is on. Using 2 slave threads.
WARNING: [XSIM 43-3431] One or more environment variables have been detected which affect the operation of the C compiler. These are typically not set in standard installations and are not tested by Xilinx, however they may be appropriate for your system, so the flow will attempt to continue.  If errors occur, try running xelab with the "-mt off -v 1" switches to see more information from the C compiler. The following environment variables have been detected:
    LIBRARY_PATH
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/akira/work/test/zeppeli/zeppeli/solution1/sim/verilog/glbl.v" into library work
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/akira/work/test/zeppeli/zeppeli/solution1/sim/verilog/AESL_axi_slave_AXILiteS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AESL_axi_slave_AXILiteS
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/akira/work/test/zeppeli/zeppeli/solution1/sim/verilog/zeppeli.autotb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module apatb_zeppeli_top
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/akira/work/test/zeppeli/zeppeli/solution1/sim/verilog/zeppeli.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module zeppeli
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/akira/work/test/zeppeli/zeppeli/solution1/sim/verilog/zeppeli_AXILiteS_s_axi.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module zeppeli_AXILiteS_s_axi
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.zeppeli_AXILiteS_s_axi
Compiling module xil_defaultlib.zeppeli
Compiling module xil_defaultlib.AESL_axi_slave_AXILiteS
Compiling module xil_defaultlib.apatb_zeppeli_top
Compiling module work.glbl
Built simulation snapshot zeppeli


****** Webtalk v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.


source /home/akira/work/test/zeppeli/zeppeli/solution1/sim/verilog/xsim.dir/zeppeli/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-186] '/home/akira/work/test/zeppeli/zeppeli/solution1/sim/verilog/xsim.dir/zeppeli/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Tue Oct 13 00:24:02 2020. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2019.2/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Tue Oct 13 00:24:02 2020...


****** xsim v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.


source xsim.dir/zeppeli/xsim_script.tcl
# xsim {zeppeli} -autoloadwcfg -tclbatch {zeppeli.tcl}
Vivado Simulator 2019.2
Time resolution is 1 ps
source zeppeli.tcl
## run all
////////////////////////////////////////////////////////////////////////////////////
// Inter-Transaction Progress: Completed Transaction / Total Transaction
// Intra-Transaction Progress: Measured Latency / Latency Estimation * 100%
//
// RTL Simulation : "Inter-Transaction Progress" ["Intra-Transaction Progress"] @ "Simulation Time"
////////////////////////////////////////////////////////////////////////////////////
// RTL Simulation : 0 / 1 [0.00%] @ "125000"
// RTL Simulation : 0 / 1 [1000000000.00%] @ "100000145000"
// RTL Simulation : 0 / 1 [2000000100.00%] @ "200000155000"
// RTL Simulation : 0 / 1 [3000000200.00%] @ "300000165000"
// RTL Simulation : 0 / 1 [4000000300.00%] @ "400000175000"
Finished C/RTL cosimulation.

Task has been canceled!

エラーの解消

問題は関数呼び出しによってbread_oに値が代入されないことによって引き起こされるので、代入されるようにすればよい。

zeppeli.cpp

#include <stdint.h>
#include <ap_int.h>
#include "zeppeli.h"

void zeppeli(
        ap_uint<1>  bread_i,
        ap_uint<8>  *bread_num_o
){
#pragma HLS INTERFACE s_axilite register port=bread_num
    static ap_uint<8> bread_num = 0;
    if(bread_i == 1){
        ++bread_num;
        *bread_num_o = bread_num;
    } else {
        *bread_num_o = bread_num;
    }
}

エラー要因解消後のcosim実行結果

終了するようになった。

INFO: [HLS 200-10] Running '/opt/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/vivado_hls'
INFO: [HLS 200-10] For user 'akira' on host 'akira-Surface-Book' (Linux_x86_64 version 5.4.0-48-generic) on Tue Oct 13 00:33:41 JST 2020
INFO: [HLS 200-10] On os Ubuntu 18.04.5 LTS
INFO: [HLS 200-10] In directory '/home/akira/work/test/zeppeli'
Sourcing Tcl script '/home/akira/work/test/zeppeli/zeppeli/solution1/cosim.tcl'
INFO: [HLS 200-10] Opening project '/home/akira/work/test/zeppeli/zeppeli'.
INFO: [HLS 200-10] Opening solution '/home/akira/work/test/zeppeli/zeppeli/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-10] Setting target device to 'xczu3eg-sbva484-1-e'
INFO: [COSIM 212-47] Using XSIM for RTL simulation.
INFO: [COSIM 212-14] Instrumenting C test bench ...
   Build using "/opt/Xilinx/Vivado/2019.2/tps/lnx64/gcc-6.2.0/bin/g++"
   Compiling apatb_zeppeli.cpp
   Compiling zeppeli.cpp_pre.cpp.tb.cpp
   Compiling tb_zeppeli.cpp_pre.cpp.tb.cpp
   Generating cosim.tv.exe
INFO: [COSIM 212-302] Starting C TB testing ...
INFO: [COSIM 212-333] Generating C post check test bench ...
INFO: [COSIM 212-12] Generating RTL test bench ...
INFO: [COSIM 212-1] *** C/RTL co-simulation file generation completed. ***
INFO: [COSIM 212-323] Starting verilog simulation.
INFO: [COSIM 212-15] Starting XSIM ...
INFO: [XSIM 43-3496] Using init file passed via -initfile option "/opt/Xilinx/Vivado/2019.2/data/xsim/ip/xsim_ip.ini".
Vivado Simulator 2019.2
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab xil_defaultlib.apatb_zeppeli_top glbl -prj zeppeli.prj -L smartconnect_v1_0 -L axi_protocol_checker_v1_1_12 -L axi_protocol_checker_v1_1_13 -L axis_protocol_checker_v1_1_11 -L axis_protocol_checker_v1_1_12 -L xil_defaultlib -L unisims_ver -L xpm --initfile /opt/Xilinx/Vivado/2019.2/data/xsim/ip/xsim_ip.ini --lib ieee_proposed=./ieee_proposed -s zeppeli
Multi-threading is on. Using 2 slave threads.
WARNING: [XSIM 43-3431] One or more environment variables have been detected which affect the operation of the C compiler. These are typically not set in standard installations and are not tested by Xilinx, however they may be appropriate for your system, so the flow will attempt to continue.  If errors occur, try running xelab with the "-mt off -v 1" switches to see more information from the C compiler. The following environment variables have been detected:
    LIBRARY_PATH
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/akira/work/test/zeppeli/zeppeli/solution1/sim/verilog/glbl.v" into library work
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/akira/work/test/zeppeli/zeppeli/solution1/sim/verilog/AESL_axi_slave_AXILiteS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AESL_axi_slave_AXILiteS
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/akira/work/test/zeppeli/zeppeli/solution1/sim/verilog/zeppeli.autotb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module apatb_zeppeli_top
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/akira/work/test/zeppeli/zeppeli/solution1/sim/verilog/zeppeli.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module zeppeli
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/akira/work/test/zeppeli/zeppeli/solution1/sim/verilog/zeppeli_AXILiteS_s_axi.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module zeppeli_AXILiteS_s_axi
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.zeppeli_AXILiteS_s_axi
Compiling module xil_defaultlib.zeppeli
Compiling module xil_defaultlib.AESL_axi_slave_AXILiteS
Compiling module xil_defaultlib.apatb_zeppeli_top
Compiling module work.glbl
Built simulation snapshot zeppeli


****** Webtalk v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.


source /home/akira/work/test/zeppeli/zeppeli/solution1/sim/verilog/xsim.dir/zeppeli/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-186] '/home/akira/work/test/zeppeli/zeppeli/solution1/sim/verilog/xsim.dir/zeppeli/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Tue Oct 13 00:34:05 2020. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2019.2/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Tue Oct 13 00:34:05 2020...


****** xsim v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.


source xsim.dir/zeppeli/xsim_script.tcl
# xsim {zeppeli} -autoloadwcfg -tclbatch {zeppeli.tcl}
Vivado Simulator 2019.2
Time resolution is 1 ps
source zeppeli.tcl
## run all
////////////////////////////////////////////////////////////////////////////////////
// Inter-Transaction Progress: Completed Transaction / Total Transaction
// Intra-Transaction Progress: Measured Latency / Latency Estimation * 100%
//
// RTL Simulation : "Inter-Transaction Progress" ["Intra-Transaction Progress"] @ "Simulation Time"
////////////////////////////////////////////////////////////////////////////////////
// RTL Simulation : 0 / 1 [0.00%] @ "125000"
// RTL Simulation : 1 / 1 [100.00%] @ "245000"
////////////////////////////////////////////////////////////////////////////////////
$finish called at time : 285 ns : File "/home/akira/work/test/zeppeli/zeppeli/solution1/sim/verilog/zeppeli.autotb.v" Line 387
## quit
INFO: [Common 17-206] Exiting xsim at Tue Oct 13 00:34:18 2020...
INFO: [COSIM 212-316] Starting C post checking ...
INFO: [COSIM 212-1000] *** C/RTL co-simulation finished: PASS ***
INFO: [COSIM 212-211] II is measurable only when transaction number is greater than 1 in RTL simulation. Otherwise, they will be marked as all NA. If user wants to calculate them, please make sure there are at least 2 transactions in RTL simulation.
Finished C/RTL cosimulation.